1. Field of the Invention
This invention relates to a transmitting circuit and a receiving circuit employing the direct-sequence spread spectrum communication system.
2. Description of the Prior Art
Transmitting and receiving circuits employing the direct-sequence spread spectrum communication system are known. This prior art transmitting circuit transmits data with spectrum of data spread by mixing input data with a chip code signal (spread code signal) having a predetermined serial data pattern. This prior art receiving circuit receives the transmitted data by the transmitting circuit mentioned above and demodulates the data with inverse spread spectrum sequence.
FIG. 8A is a block diagram of such a prior art transmitting circuit C11 employing the direct-sequence spread spectrum communication system. FIG. 8B is a block diagram of such a prior art receiving circuit C12 employing the direct-sequence spread spectrum communication system. FIG. 9 shows waveforms for explaining signals observed in respective points of this prior art transmitting circuit C11 which is also used in the description of the embodiments of this invention.
In FIG. 8A, the prior art transmitting circuit C11 comprises a chip code signal generator 56 for generating a chip code signal, a multiplexer 52 for multiplying an input data by the chip code signal, a local oscillator 57 for generating a local oscillation signal, a multiplexer 53 for multiplying an output of the multiplier 52 by the oscillation signal. An output of the multiplier 53 is transmitted by an antenna 54. The input data is subjected to the direct-sequence spectrum spreading by multiplying by the chip code signal with the multiplier 52. That is, as shown in FIG. 9. the input data as shown by waveform 201 is multiplied by the chip code signal as shown by waveform 202 with the multiplier 52 to produce a spread data signal as shown by waveform 203 of which spectrum is spread. As the chip signal, pseudnoise type signals (PN code) are popular. The multiplying the input data by this chip code signal spreads the spectrum of the input data. Generally, the chip code signal has a period natural number times a period of the data signal. In the example as shown in FIG. 9, one bit of data corresponds to one period of the chip signal.
The spread data is mixed with the local oscillation signal to be transmitted through the antenna 54.
The prior art receiving circuit C12 performs demodulation with inverse spread spectrum sequence. In FIG. 8B, the receiving circuit C12 comprises the chip code signal generator 5 for generating the chip code signal as shown by the waveform 202 which is the same signal as the output of the chip code signal generator 56 of the transmitting circuit C11, a local oscillator 4 for generating a local oscillation (carrier) signal having the same frequency as the local oscillator 57 of the transmitting circuit C11, a multiplier 3 for multiplying the local oscillation signal by the chip code signal (chip signal), a multiplier 2 for multiplying an input signal (data signal) received by an antenna 1 by the output of the multiplier 3, a lowpass filter 7 for filtering an output of the multiplier 2 to remove high frequency components, and a synchronizing circuit 6 responsive to the output of the multiplier 2 for generating an asynchronous condition signal. The local oscillator 4 generates the local oscillation signal under control of the synchronizing circuit 6. The output of the lowpass filter 7 is a demodulation signal of the input signal. The chip code signal generator 56 also performs synchronization between the input signal and the chip code signal in response to the asynchronous condition signal by phase-shifting the chip code signal having a predetermined data pattern continuously repeated.
When the chip code signal of the transmitting circuit C11 is out of phase with the chip code signal of the receiving circuit C12 or the frequency of the local oscillation signal of the transmitting circuit C11 does not agree with the local oscillation signal of the receiving circuit C12, for example, in the initial condition just after the power on condition, the original data signal cannot be demodulated. Therefore, the synchronizing circuit 6 should synchronize the chip signals of the transmitting and receiving circuits and make frequencies and timings of the local oscillation signals of the transmitting and receiving circuits equal. The synchronizing circuit 6 obtains synchronizing timings of the transmitting circuit C11 in the initial condition or the like. Then, in the following condition, namely, after synchronizing condition has been obtained, it observes the synchronizing condition and maintains this condition. When the asynchronous condition is detected the synchronizing circuit 6 and the chip code signal generation circuit 5 performs synchronization immediately.
More specifically, the synchronizing circuit 6 causes the chip code signal generation circuit 5 to synchronize the input signal with the chip code signal by consecutively phase shifting the predetermined serial data pattern continuously repeated until the data pattern is circulated once.
However, in the prior art receiving circuit C12, once the synchronizing timings are lost by crossing the transmission path between the transmitting and receiving circuits by an obstacle or the like, it takes a long period so obtain the synchronizing condition again in the direct-sequence spread spectrum communication system. Moreover, if the synchronization is obtained within a relatively short time, in the data communication, resending is required. Therefore, it takes a further long time to recover the receiving condition to the synchronous condition.
Moreover, in the prior art receiving circuit C12, when a data rate of the transmitted data is changed, another lowpass filter is necessary. Moreover, information indicative of changing the data rate should be transmitted before changing of the data rate. Such a system is inconvenient because the circuit scale is large.